(Nanowerk News) Thermoelectric materials convert a temperature gradient into a voltage. Most thermoelectrics, however, are too inefficient for widespread practical application. Still, the possibility that these materials could usefully harness heat waste, such as that generated by combustion engines, makes improving their efficiency an important pursuit in materials science. A team of scientists led by Wooyoung Lee at Yonsei University in Korea has now shown that interface roughening may be an effective way to enhance the thermoelectric properties of core/shell nanowires (“Reduction of Lattice Thermal Conductivity in Single Bi-Te Core/Shell Nanowires with Rough Interface”).
In the ideal thermoelectric, the charge conducts easily from a hot point to a cold one, while heat conduction is low. The ratio between these quantities is contained in the thermoelectric ‘figure of merit’.
Nanowires with a bismuth core encased in a tellurium shell have improved thermoelectric properties when the interface between the core and shell is roughened by impeding the flow of phonons, but not electrons.
As both electrons and vibrational waves in the lattice, known as phonons, contribute to a material’s thermal conductivity, Lee and his colleagues attempted to raise a material’s thermoelectric figure of merit by suppressing the conductivity of phonons without impairing electrical conductivity. This can be achieved by adding defects or nanostructuring a material to make it smaller than the phonon mean-free path — the typical distance a phonon travels before it scatters.
Lee and his team combined both of these tricks to reduce the thermal conductivity of a promising thermoelectric material consisting of a bismuth nanowire core coated with a tellurium shell. The team synthesized the wires by cooling just-prepared bismuth nanowires with liquid nitrogen and then coating them with tellurium using a sputtering technique, giving a core/shell structure with a smooth interface. They also prepared the wires without the cooling step, resulting in a rough interface.
After examining a series of the core/shell nanowires of 160–460 nm in diameter in both the smooth and rough versions, the researchers noticed two trends: the narrowest wires had the lowest thermal conductivity, and wires with rough interfaces had lower thermal conductivity than those with smooth interfaces — in some cases by as much as a factor of five.
According to Lee, roughening of the interface between the bismuth and tellurium reduces the thermal conductivity of phonons more significantly than electron thermal conductivity (see image). “The overall effect is to increase the thermoelectric figure of merit,” says Lee.
Source: Tokyo Institute of Technology
http://www.nanowerk.com/news/newsid=23457.php
New ’3-D’ Transistors Promising Future Chips
Researchers from Purdue and Harvard universities have created a new type of transistor made from a material that could replace silicon and have a 3-D structure instead of conventional flat computer chips.
The approach could enable engineers to build faster, more compact and efficient integrated circuits and lighter laptops that generate less heat than today’s. The transistors contain tiny nanowires made not of silicon, like conventional transistors, but from a material called indium-gallium-arsenide.
The device was created using a so-called “top-down” method, which is akin to industrial processes to precisely etch and position components in transistors. Because the approach is compatible with conventional manufacturing processes, it is promising for adoption by industry, said Peide “Peter” Ye, a professor of electrical and computer engineering at Purdue.
A new generation of silicon computer chips, due to debut in 2012, will contain transistors having a vertical structure instead of a conventional flat design. However, because silicon has a limited “electron mobility” — how fast electrons flow - other materials will likely be needed soon to continue advancing transistors with this 3-D approach, Ye said.
Indium-gallium-arsenide is among several promising semiconductors being studied to replace silicon. Such semiconductors are called III-V materials because they combine elements from the third and fifth groups of the periodic table.
“Industry and academia are racing to develop transistors from the III-V materials,” Ye said. “Here, we have made the world’s first 3-D gate-all-around transistor on much higher-mobility material than silicon, the indium-gallium-arsenide.”
Findings will be detailed in a paper to be presented during the International Electron Devices Meeting in Washington, D.C. The work is led by Purdue doctoral student Jiangjiang Gu; Harvard doctoral student Yiqun Liu; Roy Gordon, Harvard’s Thomas D. Cabot Professor of Chemistry; and Ye.
Transistors contain critical components called gates, which enable the devices to switch on and off and to direct the flow of electrical current. In today’s chips, the length of these gates is about 45 nanometers, or billionths of a meter. However, in 2012 industry will introduce silicon-based 3-D transistors having a gate length of 22 nanometers.
“Next year if you buy a computer it will have the 22-nanometer gate length and 3-D silicon transistors,” Ye said.
The 3-D design is critical because the 22-nanometer gate lengths will not work in a flat design.
“Once you shrink gate lengths down to 22 nanometers on silicon you have to do more complicated structure design,” Ye said. “The ideal gate is a necklike, gate-all-around structure so that the gate surrounds the transistor on all sides.”
The nanowires are coated with a “dielectric,” which acts as a gate. Engineers are working to develop transistors that use even smaller gate lengths, 14 nanometers, by 2015.
However, further size reductions beyond 14 nanometers and additional performance improvements are likely not possible using silicon, meaning new designs and materials will be needed to continue progress, Ye said.
“Nanowires made of III-V alloys will get us to the 10 nanometer range,” he said.
The new findings confirmed that the device made using a III-V material has the potential to conduct electrons five times faster than silicon.
Creating smaller transistors also will require finding a new type of insulating layer essential for the devices to switch off. As gate lengths shrink smaller than 14 nanometers, the silicon dioxide insulator used in conventional transistors fails to perform properly and is said to “leak” electrical charge.
One potential solution to this leaking problem is to replace silicon dioxide with materials that have a higher insulating value, or “dielectric constant,” such as hafnium dioxide or aluminum oxide.
In the new work, the researchers applied a dielectric coating made of aluminum oxide using a method called atomic layer deposition. Because atomic layer deposition is commonly used in industry, the new design may represent a practical solution to the coming limits of conventional silicon transistors.
Using atomic layer deposition might enable engineers to design transistors having thinner oxide and metal layers for the gates, possibly consuming far less electricity than silicon devices.
“A thinner dielectric layer means speed goes up and voltage requirements go down,” Ye said.
The work is funded by the National Science Foundation and the Semiconductor Research Corp. and is based at the Birck Nanotechnology Center in Purdue’s Discovery Park. The latest research is similar to, but fundamentally different from, research reported by Ye’s group in 2009. That work involved a design called a finFET, for fin field-effect transistor, which uses a finlike structure instead of the conventional flat design. The new design uses nanowires instead of the fin design.
By: Emil Venere
Source: http://www.scientificcomputing.com/news-HPC-New-3-D-Transistors-Promising-Future-Chips-121211.aspx